Fundamentals of writing an Architecture in VHDL

The basic aim of an Architecture is to obtain an output signal/s when input signal/s are applied.
It generates an output signal on the output pin (a pin which can write to) based on the input signals applied on the input pin (a pin which can be read from). The input and output pin/ports are declared in the entity part of the program.
Thus the code written inside Architecture specifies the logical relation between input and output.

An Architecture is modeled with the use of -
* Signals,variables,user defined types and operators
* Signal assignment statements
* Processes

$. Signal Assignment Statements (Implicit Process)

Signal assignment implies a process(function) that is executed in parallel when anything on the right hand side of the assignment changes.

Three types of Signal Assignment Statements are -
* Simple Signal Assignment
* Conditional Signal Assignment (When else statements)
* Selected Signal Assignment (With select statements)

$. Process

A process in VHDL architecture is a set of statements that are executed sequentially and not in parallel.
A process can be declared explicitly and the sequential statements that can be used inside a process are -
* Simple Signal Assignment
* If-Then Statements
* Case Statements
* Looping Statements
* Wait Statements


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