Getting Started with VHDL

A VHDL program consists of 4 Main Design Units

1.Entity
-It is how the system is viewed externally

2.Architecture
-It is a description of functionality (Schematic)

3.Configuration
-It assosciates Entity and Architecture

4.Package
-It is used to store a Reusable code(Library)



$. ENTITY DECLARATION SYNTAX :
 

Entity <name_of_entity> is

Generic Declarations

Port Declarations

end <name_of_entity>;

*  <name_of_entity> is any alphanumeric name given to the entity

*  Generic Declarations are used to pass information into a model

*  Port Declarations are used to describe the input,output pins



$. Port Declaration Syntax:
 

Port(
port_name1:<mode> <type> ;
port_name2:<mode> <type> ;
.
.
.
port_nameN:<mode> <type> 
);



* port_name is a name given to the port/pin

* <mode> is used to specify the direction of data flow through that pin,
                   modes are-
in         -for input
                  input signals can only be read from
out          -for output
           output signals can only be written to
inout     -bidirectional
buffer -output with internal feedback
          physically it is an output pin but can also be read

* <type> is used to specify the data type of the port
            Some of the commonly used types are-
  STD_LOGIC - Declares a Standard Logic Bit which can have values
                     0 (logic low)
                     1 (logic high)
              x (Unknown)
                     z (Tristate)
                     - (Don't Care)

  STD_LOGIC_VECTOR(m downto 0) - Declares a Standard Logic Vector of m+1 bits                    where port_name(m) signifies the MSB and port_name(0) signifies the LSB.

Note that Every port declaration ends with a semi-colon except the last one


$. ARCHITECTURE :
 
Architecture describes the internal logic of our model,the outside world can only see the port connections and the parameters passed to it.
Note: An architecture must be associated to an Entity
  Entity can have multiple architecture.


Syntax of Architecture:



Architecture <identifier> of <name_of_entity> is

Declaration of variables that aren't ports or generics

Begin
.
.
.
Body of Architecture 
.
.
.
End Architecture <identifier> ;

* <identifier> is the name given to the architecture
* Variables that aren't ports or generics are declared before Begin
   these variables are generally Temporary Signals or Constants for interconnections.
* Body of Architecture is the description of functionality and timing of the model.
    It consists of executable statements


Next : Fundamentals of  writing an architecture in VHDL